Interrupts

This is step 8 of the book Writing a RISC-V Emulator from Scratch in 10 Steps, whose goal is running xv6, a small Unix-like OS, in your emulator in the final step.

The source code is available at d0iasm/rvemu-for-book/step08/.

Goal of This Page

In the end of this page, we support interrupts, external asynchronous events that may cause a hardware thread to experience an unexpected transfer of control.